1. Field of the Invention
The present invention relates to a photoelectric converting device for use in an image input apparatus such as video camera, facsimile apparatus, copying machine or image reader, or in an image information processing apparatus such as a range finder of a camera, and more particularly a photoelectric converting device integrally provided with a phototransistor and a transistor for refreshing or resetting said phototransistor.
2. Related Background Art
In the field of photoelectric converting devices having resetting transistors integrally with phototransistors on a same semiconductor substrate, there are already known structures as disclosed in the U.S. Pat. No. 4,791,469 allowed to Tadahiro Ohmi et al., in the U.S. Pat. No. 4,794,443 allowed to Nobuyoshi Tanaka et al., and in the U.S. Pat. No. 4,866,293 allowed to Yoshio Nakamura et al.
FIG. 1A is a schematic cross-sectional view of a conventional photoelectric converting device.
Referring to FIG. 1A, an n.sup.31 -layer 102 is formed by epitaxial growth on an n-type semiconductor substrate 101, and said layers 101 and 102 constitute a collector area in each cell. In each cell there is formed a p-base area 103, in which an n.sup.+ -emitter area 104 is formed to constitute an npn bipolar transistor (BPT) serving as a phototransistor.
In the p-base area 103 there is also formed a p.sup.+ -source area 105. Also at a certain distance a p.sup.+ -drain area 106 is formed in the n.sup.- -layer 102, and a gate electrode 108 is formed on an oxide film 107 to constitute a resetting p-channel MOS transistor (reset Tr).
Above the bipolar transistor and the resetting transistor, there are formed an insulation film 109, a drain electrode 110 connected to the drain area 106, and an emitter electrode 111 connected to the n+-emitter area 104. On these components there is formed an insulation film 112, which is covered by an opaque film 113 except for an aperture. On the bottom side of the substrate 101 there is formed a collector electrode 114.
FIG. 1B is an equivalent circuit diagram of the above-explained photoelectric converting device, in which shown are the collector 201 of the bipolar transistor; collector electrode 202; base 203 of the bipolar transistor; emitter 204 of the bipolar transistor; emitter electrode 205; resetting transistor 206; terminal 207 connected to the drain electrode; and terminal 208 connected to the gate electrode.
In the following there will be explained the basic function, with reference to the equivalent circuit shown in FIG. 1B. It is assumed that the base 203 of the bipolar transistor is in an initial state with a predetermined potential. Then light enters the bipolar transistor, whereby carriers of an amount corresponding to the received amount of light are accumulated in the base 203 (accumulating operation). The potential of the base varies depending on the charge accumulated in the base, and the current between the emitter and collector is controlled by said potential change.
Then an electrical signal corresponding to the amount of incident light is read from the emitter electrode 205 in the floating state (readout operation).
The removal of the carriers accumulated in the base 203 (refreshing operation) is conducted by grounding the emitter electrode 205 and setting the base 203 at the initial base potential through the MOS transistor 206. The carriers in the base area can be dissipated by setting the terminal 207 in advance at a potential corresponding to said initial base potential and turning on the refreshing transistor 206 at the refreshing operation.
Thereafter the operations of accumulation, readout and refreshing are repeated in a similar manner.
As explained above, the photoelectric converting device shown in FIGS. 1A and 1B accumulates the carriers, generated by light irradiation, in the base area and controls the current between the emitter and collector electrodes by the amount of accumulated charge. Such photoelectric converting device can achieve high output, high sensitivity and low noise because the accumulated carriers are read after charge amplification by the bipolar transistor.
Also the potential V.sub.p of the base area generated by the photoexcited carriers accumulated therein is represented by Q/C, wherein Q is the amount of charge of the carriers accumulated in the base while C is the capacitance connected to the base. With a higher level of integration of the photoelectric converting device, both Q and C decrease with the reduction in cell size. Thus the potential V.sub.p generated by photoexcitation remains almost constant even when the level of integration is such photoelectric converting device is improved. Consequently such device is advantageous also for a higher level of resolving power in the future.
In such conventional photoelectric converting device as explained above, the collector area of the bipolar transistor and the channel forming area of the resetting transistor are integrally formed as an n.sup.- -area 102. Consequently the impurity concentration of said collector area of the bipolar transistor is same as that of said channel forming area of the resetting transistor.
More specifically, the impurity concentration in the collector area of the bipolar transistor is strongly related with the photosensitivity of the photoelectric converting device and with the KTC noise thereof, and is generally considered preferably within a range from 8.times.10.sup.13 to 5.times.10.sup.15 cm.sup.-3.
However such conventional photoelectric converting device has been associated with the following drawbacks:
(1) During the accumulating operation, the resetting transistor has to be turned off, and, in order to avoid the leak current between the source and drain of the resetting transistor, there is required a sufficiently long gate, which leads to an increased chip size. This is presumably due to an excessively low impurity concentration in the channel forming area of the resetting transistor; PA1 (2) A BT stress test, applying a voltage to the gate of the resetting transistor, shows a larger fluctuation of the threshold voltage V.sub.th than in the ordinary MOS transistors. Although the reason for this phenomenon is not yet clear, it is presumably due to a fact that a Poule-Frenkel trap generated by inversion at the oxide film-silicon interface is filled with carriers, thus shifting the threshold voltage V.sub.th in a direction facilitating the flow of current; PA1 (3) Because of the low impurity concentration in the channel forming area of the resetting transistor, a concentration in the electric field easily induces a change in the form of PN junctions between the channel forming area and the source and drain areas and results in so-called walking phenomenon of increases in the voltage resistance and the threshold voltage V.sub.th with time, so that the performance of the resetting transistor is inevitably unstable.
It is therefore conceivable, as described in the above-mentioned U.S. Pat. No. 4,791,469, to prevent the leak current by impurity doping in a part, where the inversion layer is formed, of the channel. Such structure is shown in FIG. 1C, in which 102' indicates a channel portion doped with impurity.
However such channel doping alone is unable to sufficiently solve the technical drawbacks, because of the following fact, as identified by many experiments conducted by the present inventors.
Because the resetting MOS transistor is integrally constructed with the phototransistor, the usual parameters of gate length, gate width and threshold voltage in the isolated MOS transistor cannot be applied to such resetting transistor. More specifically, since the n.sup.- -layer 102 of low impurity concentration and the n-layer 102 under the application of the collector voltage are positioned below the channel, the depletion layers DL become mutually connected in a position PT deeper than the drain area 106 and the source (base) area 105 as shown in FIG. 1C, thus causing a punch-through phenomenon.